EPM3256AQC208-10 vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3256AQC208-10 by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3256AQC208-10N

EPM3256AQC208-10N - 256-Macro MAX 3000A 3.3V CPLD | Altera

EPM3256AQC208-10N Obsolete

Specification Comparison

Parameter EPM3256AQC208-10 EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.20 $4.62
Family MAX 3000A β€”
Logic Family CMOS (EEPROM-based) β€”
Macrocells 256 β€”
Usable Gates 5,000 10,000
User I/Os 161 β€”
Number of Pins 208 β€”
Package 208-BFQFP (PQFP, Gull Wing) β€”
Pin-to-Pin Propagation Delay 10 ns β€”
Counter Frequency (max) 227.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Tolerance MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant 5 V tolerant, MultiVolt interface
Programming Interface IEEE 1149.1 JTAG (ISP) β€”
Operating Temperature 0 Β°C to +70 Β°C (Commercial) 0C to +70C (Commercial)
PCI-SIG Compliance Yes (speed grades -4, -5, -6, -7, -10) β€”
Global Clock Networks 4 (CLK, CLR, OE, GCLK) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Maximum Counter Frequency β€” 227.3 MHz
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance β€” IEEE Std. 1532
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)

Datasheets & Resources

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