EPM3256AQC208-10 vs EPM3512AQC208-10 Comparison
Detailed side-by-side comparison of EPM3256AQC208-10 by Altera and EPM3512AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoleteSpecification Comparison
| Parameter | EPM3256AQC208-10 | EPM3512AQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.20 | $22.10 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | β |
| Macrocells | 256 | 512 |
| Usable Gates | 5,000 | 10,000 |
| User I/Os | 161 | 208 |
| Number of Pins | 208 | β |
| Package | 208-BFQFP (PQFP, Gull Wing) | 208-pin PQFP |
| Pin-to-Pin Propagation Delay | 10 ns | β |
| Counter Frequency (max) | 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Tolerance | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant | β |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) | 0C to +70 C (commercial) |
| PCI-SIG Compliance | Yes (speed grades -4, -5, -6, -7, -10) | β |
| Global Clock Networks | 4 (CLK, CLR, OE, GCLK) | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified data] |
| Logic Array Blocks (LABs) | β | 32 |
| Propagation Delay (tPD) | β | 7.5 ns |
| Maximum Frequency (fCNT) | β | 116.3 MHz |
| Configuration Memory | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | β | Yes (IEEE 1149.1) |
| PCI Compliance | β | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |