EPM3256AQC208-10N vs EPM3256AFC256-10N Comparison

Detailed side-by-side comparison of EPM3256AQC208-10N by Altera and EPM3256AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AQC208-10N EPM3256AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $4.62 $25.95
Series MAX 3000A β€”
Programmable Type In-System Programmable (EEPROM) β€”
Number of Macrocells 256 β€”
Number of Logic Elements/Blocks 16 LABs β€”
Usable Gates 10,000 5,000 gates
Number of I/O Pins 161 (158 user I/O per Arrow listing) β€”
Propagation Delay (tpd) 10 ns (max) β€”
Maximum Counter Frequency 227.3 MHz 227.3 MHz
Supply Voltage - Internal 3.0 V to 3.6 V (3.3 V typical) β€”
Operating Temperature 0C to +70C (Commercial) 0 C to 70 C (commercial)
Package / Case 208-BFQFP / 208-PQFP (28x28 mm) β€”
Mounting Type Surface Mount β€”
ISP Compliance IEEE Std. 1532 β€”
Boundary Scan IEEE Std. 1149.1 (JTAG) β€”
I/O Tolerance 5 V tolerant, MultiVolt interface β€”
RoHS Status [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] β€”
Family β€” MAX 3000A
Device Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 256
Maximum User I/O β€” 161
Pin-to-Pin Logic Delay β€” 10 ns
Core Voltage β€” 3.3 V
I/O Logic Level Compatibility β€” 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE 1532 / JTAG (TDI, TDO, TMS, TCK)
Package β€” 256-pin FineLine BGA
Logic Family β€” CMOS
PCI Compliance β€” PCI Local Bus Specification Rev 2.2 (at -10 grade)

Datasheets & Resources

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