EPM3256AQC208-10N vs EPM3512AQC208-10-10N Comparison
Detailed side-by-side comparison of EPM3256AQC208-10N by Altera and EPM3512AQC208-10-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N ObsoleteSpecification Comparison
| Parameter | EPM3256AQC208-10N | EPM3512AQC208-10-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.62 | $31.20 |
| Series | MAX 3000A | β |
| Programmable Type | In-System Programmable (EEPROM) | β |
| Number of Macrocells | 256 | β |
| Number of Logic Elements/Blocks | 16 LABs | β |
| Usable Gates | 10,000 | 10,000 |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | β |
| Propagation Delay (tpd) | 10 ns (max) | β |
| Maximum Counter Frequency | 227.3 MHz | β |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | β |
| Operating Temperature | 0C to +70C (Commercial) | 0 Β°C to +70 Β°C (commercial) |
| Package / Case | 208-BFQFP / 208-PQFP (28x28 mm) | β |
| Mounting Type | Surface Mount | Surface Mount |
| ISP Compliance | IEEE Std. 1532 | β |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | β |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | β |
| RoHS Status | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | β |
| Family | β | MAX 3000A |
| Macrocells | β | 512 |
| User I/Os | β | 172 |
| Logic Elements / LABs | β | 16 Logic Array Blocks |
| Propagation Delay (tPD) | β | 10 ns (-10 speed grade) |
| Maximum Frequency (fCNT) | β | 87 MHz |
| Supply Voltage - Core (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V |
| Process Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes, IEEE Std. 1532 compliant |
| Boundary-Scan (JTAG) | β | Yes, IEEE 1149.1 |
| PCI-SIG Compliance | β | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) |
| Package | β | 208-pin PQFP (Plastic Quad Flat Pack) |
| Lead-Free / RoHS | β | [DATA_NEEDED: RoHS status] |