EPM3256AQC208-10N vs EPM3512AQC208-3N Comparison

Detailed side-by-side comparison of EPM3256AQC208-10N by Altera and EPM3512AQC208-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AQC208-10N EPM3512AQC208-3N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $4.62 $16.40
Series MAX 3000A β€”
Programmable Type In-System Programmable (EEPROM) β€”
Number of Macrocells 256 β€”
Number of Logic Elements/Blocks 16 LABs β€”
Usable Gates 10,000 β€”
Number of I/O Pins 161 (158 user I/O per Arrow listing) β€”
Propagation Delay (tpd) 10 ns (max) β€”
Maximum Counter Frequency 227.3 MHz β€”
Supply Voltage - Internal 3.0 V to 3.6 V (3.3 V typical) β€”
Operating Temperature 0C to +70C (Commercial) 0C to +70C (commercial)
Package / Case 208-BFQFP / 208-PQFP (28x28 mm) β€”
Mounting Type Surface Mount Surface Mount
ISP Compliance IEEE Std. 1532 IEEE Std. 1532
Boundary Scan IEEE Std. 1149.1 (JTAG) β€”
I/O Tolerance 5 V tolerant, MultiVolt interface β€”
RoHS Status [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] [DATA_NEEDED: not stated in retrieved snippets]
Family β€” MAX 3000A
Macrocells β€” 512
User I/O Pins β€” 172
Logic Array Blocks (LABs) β€” 16
Macrocells per LAB β€” 32
Pin-to-Pin Logic Delay β€” 3 ns (speed grade -3)
Global Clock Setup Time β€” [DATA_NEEDED: actual tSU at 3 ns grade]
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Package β€” PQFP-208
Programming Technology β€” EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan β€” IEEE 1149.1 compliant
Lead-Free / Halogen-Free β€” [DATA_NEEDED]

Datasheets & Resources

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