EPM3256ATC144-10N vs EPM3256AT1144-10S Comparison
Detailed side-by-side comparison of EPM3256ATC144-10N by Altera and EPM3256AT1144-10S by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N β Last Time Buy
Specification Comparison
| Parameter | EPM3256ATC144-10N | EPM3256AT1144-10S |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.50 | $21.30 |
| Series | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | β |
| Usable Gates | 5,000 (up to 10,000 usable in family) | β |
| Number of I/Os | 116 | β |
| Number of Logic Elements / Blocks | 16 LABs | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency | 227.3 MHz | β |
| Global Clocks | 3 | β |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | β |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | β |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | β |
| ISP Compliance | IEEE Std. 1532 | β |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | β |
| Package | 144-LQFP (TQFP, ATC suffix) | TQFP-144 |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0C to +85C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | β |
| Family | β | MAX 3000A |
| Macrocells | β | 256 |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage - Core | β | 3.3 V |
| I/O Voltage Support | β | 2.5V / 3.3V / 5.0V MultiVolt |
| Programmable Interconnect | β | EEPROM-based, non-volatile |
| In-System Programming | β | Yes, via IEEE 1149.1 JTAG |
| Configuration Cells | β | EEPROM (instant-on, no external PROM) |