EPM3256ATC144-7 vs EPM3256ATC144-7N Comparison
Detailed side-by-side comparison of EPM3256ATC144-7 by Altera and EPM3256ATC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3256ATC144-7 | EPM3256ATC144-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.06 | $17.20 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 256 | β |
| User I/Os | 116 | 116 |
| Logic Elements / Gates | 600 to 10,000 usable gates | β |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Counter Frequency (fCNT) | 227.3 MHz | β |
| Speed Grade | -7 | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V | β |
| In-System Programming | IEEE Std. 1532 compliant, 3.3 V ISP | β |
| Package | TQFP-144 (LFQFP, gull-wing) | 144-pin TQFP |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Pin Count | 144 | β |
| Mounting Type | Surface Mount | Surface Mount |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) | β |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | IEEE 1149.1 boundary-scan |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Macro Cells | β | 256 |
| Logic Gates (usable) | β | 5,000 |
| Number of Logic Array Blocks (LABs) | β | 16 |
| Maximum Internal Frequency | β | 126.6 MHz |
| Supply Voltage (VCCIO) | β | 3.0 V to 3.6 V |
| Programmable Logic Technology | β | CMOS EEPROM-based |
| In-System Programmable (ISP) | β | Yes (3.3 V) |
| Logic Family | β | CMOS |
| RoHS Status | β | Compliant |