EPM3512AFC256-18 vs EPM3256AFC256-10 Comparison

Detailed side-by-side comparison of EPM3512AFC256-18 by Altera and EPM3256AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-18 EPM3256AFC256-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $17.20 $19.95
Family MAX 3000A MAX 3000A
Macrocells 512 β€”
Logic Array Blocks (LABs) 16 16 (16 macrocells each)
Maximum User I/O Pins 212 β€”
Pin-to-Pin Delay (tPD1) 18 ns β€”
Global Clock Networks 4 β€”
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) β€”
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) β€”
Operating Temperature [DATA_NEEDED: industrial/commercial grade] 0Β°C to +70Β°C (Commercial)
Programming Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) β€”
Package 256-ball FineLine BGA (FCBGA) 256-ball FBGA (Fine-Line BGA)
Ball Pitch 1.0 mm β€”
RoHS Status [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS compliance status]
Mounting Type Surface Mount Surface Mount
Logic Family β€” CMOS (EEPROM-based)
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 256
Usable Gates β€” 5,000
Maximum User I/Os β€” 161
Propagation Delay (tPD) β€” 10 ns
Internal Counter Frequency (fCNT) β€” 95.2 MHz
Supply Voltage (VCCINT) β€” 3.3 V
I/O Voltage Tolerance β€” 5.0 V tolerant
In-System Programmability β€” Yes (3.3 V ISP via JTAG IEEE 1149.1)
Pitch β€” [DATA_NEEDED: BGA ball pitch]

Datasheets & Resources

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