EPM3512AFC256-18 vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3512AFC256-18 by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 Obsolete
Specification Comparison
| Parameter | EPM3512AFC256-18 | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.20 | $17.50 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | β |
| Pin-to-Pin Delay (tPD1) | 18 ns | β |
| Global Clock Networks | 4 | β |
| VCCINT (Core Supply) | 3.0 V to 3.6 V (3.3 V typical) | β |
| VCCIO (I/O Supply) | 2.5 V or 3.3 V (MultiVolt) | β |
| Operating Temperature | [DATA_NEEDED: industrial/commercial grade] | β |
| Programming Technology | EEPROM (non-volatile) | β |
| In-System Programming | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) | β |
| Package | 256-ball FineLine BGA (FCBGA) | 256-pin FBGA |
| Ball Pitch | 1.0 mm | β |
| RoHS Status | [DATA_NEEDED: not specified in retrieved data] | unknown |
| Mounting Type | Surface Mount | Surface Mount |
| Usable Gates | β | 10,000 |
| Maximum I/O Pins | β | 208 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 87 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Voltage Tolerance | β | 5-V tolerant |
| Programmable Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Operating Temperature Range | β | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin Count | β | 256 |
| Architecture | β | MAX (Multiple Array matriX) EEPROM-based |