EPM3512AFC256-18 vs EPM3512AFC256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256-18 by Altera and EPM3512AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-18 EPM3512AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $17.20 $43.22
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum User I/O Pins 212 β€”
Pin-to-Pin Delay (tPD1) 18 ns β€”
Global Clock Networks 4 β€”
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) 3.3 V
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) 3.3 V or 2.5 V
Operating Temperature [DATA_NEEDED: industrial/commercial grade] β€”
Programming Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) β€”
Package 256-ball FineLine BGA (FCBGA) 256-ball FBGA (17 mm x 17 mm)
Ball Pitch 1.0 mm β€”
RoHS Status [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS status]
Mounting Type Surface Mount Surface Mount (BGA)
Usable Gates β€” 10000
User I/O Pins β€” 208
Operating Frequency (fMAX) β€” [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) β€” 10 ns
Setup Time (tSU) β€” 4.5 ns
Technology β€” CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) β€” 0 C to +70 C
ISP Interface β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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