EPM3512AFC256-18 vs EPM3512AFC256-19 Comparison

Detailed side-by-side comparison of EPM3512AFC256-18 by Altera and EPM3512AFC256-19 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-18 EPM3512AFC256-19
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $17.20 $10.85
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 β€”
Pin-to-Pin Delay (tPD1) 18 ns β€”
Global Clock Networks 4 β€”
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) β€”
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) β€”
Operating Temperature [DATA_NEEDED: industrial/commercial grade] -40C to +85C (industrial)
Programming Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) β€”
Package 256-ball FineLine BGA (FCBGA) 256-ball FineLine BGA (FC)
Ball Pitch 1.0 mm β€”
RoHS Status [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS status]
Mounting Type Surface Mount Surface Mount
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 10000
Maximum Operating Frequency β€” 80 MHz
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Speed Grade β€” -19
User I/O Pins β€” 208
Supply Voltage VCCINT β€” 3.3 V
I/O Supply Voltage VCCIO β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
Programming Interface β€” JTAG (IEEE 1149.1) / ISP (IEEE 1532)
Process Technology β€” 0.30 Β΅m CMOS EEPROM
Non-volatile Configuration β€” Yes (EEPROM-based)

Datasheets & Resources

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