EPM3512AFC256-18 vs EPM3512AFC256-20 Comparison

Detailed side-by-side comparison of EPM3512AFC256-18 by Altera and EPM3512AFC256-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-18 EPM3512AFC256-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $17.20 $9.75
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 212 β€”
Pin-to-Pin Delay (tPD1) 18 ns β€”
Global Clock Networks 4 β€”
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) β€”
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) β€”
Operating Temperature [DATA_NEEDED: industrial/commercial grade] [DATA_NEEDED: operating temperature range]
Programming Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) β€”
Package 256-ball FineLine BGA (FCBGA) 256-ball FBGA (Fine-pitch BGA)
Ball Pitch 1.0 mm β€”
RoHS Status [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS compliance status]
Mounting Type Surface Mount Surface Mount
Typical Usable Gates β€” 10,000
Speed Grade β€” -20 (20 ns tPD)
Pin Count β€” 256
Operating Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards β€” LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type β€” EEPROM (non-volatile)
In-System Programmability β€” Yes (JTAG IEEE 1149.1)
JTAG Support β€” Yes (boundary-scan + ISP)
MSL Level β€” [DATA_NEEDED: MSL moisture sensitivity level]
Configuration Memory β€” Internal EEPROM

Datasheets & Resources

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