EPM3512AFC256-2 vs EPM3512AFC256-18 Comparison

Detailed side-by-side comparison of EPM3512AFC256-2 by Altera and EPM3512AFC256-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-2 EPM3512AFC256-18
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $14.85 $17.20
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 212
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] β€”
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] β€”
Core Supply Voltage 3.3 V β€”
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) β€”
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant β€”
Package BGA-256 (FineLine BGA) 256-ball FineLine BGA (FCBGA)
Ball Pitch 1.0 mm 1.0 mm
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster β€”
Process Technology 0.30 um CMOS EEPROM β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial grade]
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: not specified in retrieved data]
Speed Grade -2 β€”
Pin-to-Pin Delay (tPD1) β€” 18 ns
Global Clock Networks β€” 4
VCCINT (Core Supply) β€” 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) β€” 2.5 V or 3.3 V (MultiVolt)
Programming Technology β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
Mounting Type β€” Surface Mount

Datasheets & Resources

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