EPM3512AFC256-20 vs EPM3512AFC256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256-20 by Altera and EPM3512AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-20 EPM3512AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $43.22
Family MAX 3000A MAX 3000A
Macrocells 512 512
Typical Usable Gates 10,000 β€”
Speed Grade -20 (20 ns tPD) β€”
Package 256-ball FBGA (Fine-pitch BGA) 256-ball FBGA (17 mm x 17 mm)
Pin Count 256 β€”
Operating Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) β€”
I/O Voltage (VCCIO) 2.5 V or 3.3 V (5.0 V tolerant inputs) β€”
I/O Standards LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant β€”
Program Memory Type EEPROM (non-volatile) β€”
In-System Programmability Yes (JTAG IEEE 1149.1) β€”
JTAG Support Yes (boundary-scan + ISP) β€”
Mounting Type Surface Mount Surface Mount (BGA)
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
MSL Level [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: MSL rating]
Configuration Memory Internal EEPROM β€”
Usable Gates β€” 10000
User I/O Pins β€” 208
Logic Array Blocks (LABs) β€” [DATA_NEEDED: number of LABs]
Operating Frequency (fMAX) β€” [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) β€” 10 ns
Setup Time (tSU) β€” 4.5 ns
VCCINT (Core Supply) β€” 3.3 V
VCCIO (I/O Supply) β€” 3.3 V or 2.5 V
Technology β€” CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) β€” 0 C to +70 C
ISP Interface β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532

Datasheets & Resources

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