EPM3512AFC256-22 vs EPM3512AFC256-20 Comparison

Detailed side-by-side comparison of EPM3512AFC256-22 by Intel and EPM3512AFC256-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-22 EPM3512AFC256-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.10 $9.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 208 (typical for FC256 package) β€”
Speed Grade -22 (tPD ~22 ns) -20 (20 ns tPD)
Propagation Delay (tPD) 22 ns β€”
Supply Voltage VCCINT 3.3 V β€”
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) β€”
In-System Programming IEEE Std. 1532-compliant ISP via JTAG β€”
Configuration Memory On-chip EEPROM (non-volatile) Internal EEPROM
Package FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FBGA (Fine-pitch BGA)
Mounting Type Surface Mount (BGA) Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Typical Usable Gates β€” 10,000
Pin Count β€” 256
Operating Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards β€” LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type β€” EEPROM (non-volatile)
In-System Programmability β€” Yes (JTAG IEEE 1149.1)
JTAG Support β€” Yes (boundary-scan + ISP)
MSL Level β€” [DATA_NEEDED: MSL moisture sensitivity level]

Datasheets & Resources

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