EPM3512AFC256-23 vs EPM3256AFC256-10 Comparison

Detailed side-by-side comparison of EPM3512AFC256-23 by Altera and EPM3256AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-23 EPM3256AFC256-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $15.75 $19.95
Family MAX 3000A MAX 3000A
Macrocells 512 β€”
Usable Gates 10,000 5,000
Logic Array Blocks (LABs) 16 (32 macrocells each) 16 (16 macrocells each)
Maximum Operating Frequency 178.6 MHz β€”
Propagation Delay (tPD) 5.5 ns 10 ns
Pin-to-Pin Delay 23 ns β€”
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) β€”
User I/O Pins [DATA_NEEDED: user I/O count for FC256] β€”
Package 256-ball FineLine BGA (FC256), 17 mm x 17 mm 256-ball FBGA (Fine-Line BGA)
Programming Interface JTAG (IEEE Std. 1149.1) / ISP β€”
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] 0Β°C to +70Β°C (Commercial)
Mounting Type Surface Mount (BGA) Surface Mount
Logic Family β€” CMOS (EEPROM-based)
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 256
Maximum User I/Os β€” 161
Internal Counter Frequency (fCNT) β€” 95.2 MHz
I/O Voltage Tolerance β€” 5.0 V tolerant
In-System Programmability β€” Yes (3.3 V ISP via JTAG IEEE 1149.1)
Pitch β€” [DATA_NEEDED: BGA ball pitch]
RoHS Status β€” [DATA_NEEDED: RoHS compliance status]

Datasheets & Resources

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