EPM3512AFC256-3N vs EPM3512AFC256-10 Comparison

Detailed side-by-side comparison of EPM3512AFC256-3N by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AFC256-3N EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N βœ“ Active

Specification Comparison

Parameter EPM3512AFC256-3N EPM3512AFC256-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $23.40 $17.50
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 10,000 10,000
Logic Array Blocks (LABs) 16 16
Maximum Operating Frequency 116.3 MHz β€”
Pin-to-Pin Delay (tPD) 3.5 ns (speed grade -3) 10 ns
Speed Grade -3 (slowest in family) β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) β€”
Package 256-ball FineLine BGA (FC-256) 256-pin FBGA
Mounting Type Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP β€”
Configuration Memory Non-volatile EEPROM β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] unknown
Maximum I/O Pins β€” 208
Maximum Counter Frequency β€” 87 MHz
Supply Voltage (VCCINT) β€” 3.3 V
I/O Voltage Tolerance β€” 5-V tolerant
Programmable Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532)
Operating Temperature Range β€” [DATA_NEEDED: industrial/commercial operating temperature range]
Pin Count β€” 256
Architecture β€” MAX (Multiple Array matriX) EEPROM-based

Datasheets & Resources

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