EPM3512AFC256-5C vs EPM3512AFC256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256-5C by Altera and EPM3512AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-5C EPM3512AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $28.95 $43.22
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 10,000 10000
Maximum Operating Frequency 95.2 MHz β€”
Pin-to-Pin Delay (tPD) 5 ns 10 ns
Supply Voltage - Core (VCCINT) 3.3 V β€”
I/O Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) β€”
User I/O Pins 212 (max) 208
Package 256-ball FBGA, 17 mm Γ— 17 mm, 1.0 mm pitch 256-ball FBGA (17 mm x 17 mm)
Operating Temperature 0 Β°C to +70 Β°C (commercial, "C" grade) β€”
Programming Interface IEEE Std. 1532 / JTAG (4-wire) in-system programmable β€”
Mounting Type Surface Mount Surface Mount (BGA)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Technology EEPROM-based macrocell, non-volatile CMOS EEPROM-based, non-volatile
Logic Array Blocks (LABs) β€” [DATA_NEEDED: number of LABs]
Operating Frequency (fMAX) β€” [DATA_NEEDED: fMAX MHz]
Setup Time (tSU) β€” 4.5 ns
VCCINT (Core Supply) β€” 3.3 V
VCCIO (I/O Supply) β€” 3.3 V or 2.5 V
Operating Temperature (Commercial) β€” 0 C to +70 C
ISP Interface β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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