EPM3512AFC256-5C vs EPM3512AFC256C Comparison
Detailed side-by-side comparison of EPM3512AFC256-5C by Altera and EPM3512AFC256C by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C β Last Time BuySpecification Comparison
| Parameter | EPM3512AFC256-5C | EPM3512AFC256C |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.95 | $27.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | β |
| Maximum Operating Frequency | 95.2 MHz | β |
| Pin-to-Pin Delay (tPD) | 5 ns | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | β |
| User I/O Pins | 212 (max) | β |
| Package | 256-ball FBGA, 17 mm Γ 17 mm, 1.0 mm pitch | 256-ball FineLine BGA (FC) |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial, "C" grade) | 0C to +70C (Commercial) |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Technology | EEPROM-based macrocell, non-volatile | β |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/Os | β | 208 |
| Dedicated Input Pins | β | 12 |
| Speed Grade | β | C (per datasheet ordering code) |
| Configuration Technology | β | EEPROM (non-volatile, instant-on) |
| Core Voltage | β | 3.3 V |
| I/O Standards Supported | β | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | β | IEEE 1149.1 Boundary Scan |
| PCI Compliance | β | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | β | In-system programmable via JTAG |