EPM3512AFC256-7 vs EPM3512AFC256-3N Comparison
Detailed side-by-side comparison of EPM3512AFC256-7 by Intel and EPM3512AFC256-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 β Last Time BuySpecification Comparison
| Parameter | EPM3512AFC256-7 | EPM3512AFC256-3N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $58.40 | $23.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 212 | β |
| Usable Gates | 10,000 | 10,000 |
| Pin-to-Pin Logic Delay | 7.5 ns | β |
| Counter Frequency (max) | 227.3 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | β |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | β |
| Package | 256-ball FineLine BGA (FBGA-256) | 256-ball FineLine BGA (FC-256) |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature grade] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM |
| Maximum Operating Frequency | β | 116.3 MHz |
| Pin-to-Pin Delay (tPD) | β | 3.5 ns (speed grade -3) |
| Speed Grade | β | -3 (slowest in family) |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Programming Interface | β | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP |