EPM3512AFC256C vs EPM3512AFC256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256C by Intel and EPM3512AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM3512AFC256C EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera

EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera

EPM3512AFC256C ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AFC256C EPM3512AFC256-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.95 $43.22
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum User I/Os 208 β€”
Dedicated Input Pins 12 β€”
Package 256-ball FineLine BGA (FC) 256-ball FBGA (17 mm x 17 mm)
Operating Temperature 0C to +70C (Commercial) β€”
Speed Grade C (per datasheet ordering code) β€”
Configuration Technology EEPROM (non-volatile, instant-on) β€”
Core Voltage 3.3 V β€”
I/O Standards Supported MultiVolt: 5.0 V, 3.3 V, 2.5 V β€”
JTAG Support IEEE 1149.1 Boundary Scan β€”
PCI Compliance PCI SIG Local Bus Specification Revision 2.2 β€”
Programming In-system programmable via JTAG β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Mounting Type Surface Mount Surface Mount (BGA)
Usable Gates β€” 10000
User I/O Pins β€” 208
Operating Frequency (fMAX) β€” [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) β€” 10 ns
Setup Time (tSU) β€” 4.5 ns
VCCINT (Core Supply) β€” 3.3 V
VCCIO (I/O Supply) β€” 3.3 V or 2.5 V
Technology β€” CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) β€” 0 C to +70 C
ISP Interface β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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