EPM3512AQ208-10N vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQ208-10N by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQ208-10N

EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera

EPM3512AQ208-10N βœ“ Active
Altera
EPM3512AQC208-10NS

EPM3512AQC208-10NS - MAX 3000A 512-Macro CPLD, 208-PQFP | Altera

EPM3512AQC208-10NS βœ“ Active

Specification Comparison

Parameter EPM3512AQ208-10N EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $21.40 $32.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 β€”
Usable Gates 10,000 10,000
User I/Os 172 172
Logic Array Blocks (LABs) 32 12
Package 208-pin PQFP 208-pin PQFP
Speed Grade -10 (10 ns pin-to-pin delay) β€”
Pin-to-Pin Delay (tPD) 4.5 ns (typical) 10 ns (speed grade -10)
Maximum Frequency (fCNT) 227.3 MHz β€”
Core Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 2.5 V, 3.3 V, or 5.0 V 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Process Technology CMOS EEPROM β€”
Programming Interface IEEE Std. 1532 (JTAG) ISP β€”
Operating Temperature (Industrial) -40 C to +85 C β€”
Mounting Type Surface Mount Surface Mount
RoHS Status unknown [DATA_NEEDED: rohs status]
Macro Cells β€” 512
Internal Counter Frequency β€” 227.3 MHz max
Propagation Delay β€” 7.5 ns (datasheet figure)
Logic Family β€” CMOS, EEPROM-based
Configuration β€” Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
Operating Temperature β€” 0C to +70C (commercial)
ISP Standard β€” IEEE Std. 1532

Datasheets & Resources

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