EPM3512AQC20-10 vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC20-10 by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC20-10 EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $21.10 $32.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 β€”
Logic Array Blocks (LABs) 16 12
Macrocells per LAB 32 β€”
User I/O Pins 100 β€”
Pin-to-Pin Delay (tPD) 10 ns 10 ns (speed grade -10)
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage VCCINT 5.0 V β€”
MultiVolt I/O Voltages 5.0 V / 3.3 V / 2.5 V / 1.8 V β€”
Programming Interface IEEE 1149.1 (JTAG) - In-System Programmable β€”
Process Technology 0.30 Β΅m EEPROM CMOS β€”
Package PQFP-240 (QC20 designation per Altera ordering code) 208-pin PQFP
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
RoHS Status Compliant (lead-free PQFP package) [DATA_NEEDED: rohs status]
Macro Cells β€” 512
Usable Gates β€” 10,000
User I/Os β€” 172
Internal Counter Frequency β€” 227.3 MHz max
Propagation Delay β€” 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Logic Family β€” CMOS, EEPROM-based
Configuration β€” Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
ISP Standard β€” IEEE Std. 1532
Mounting Type β€” Surface Mount

Datasheets & Resources

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