EPM3512AQC208-10-10N vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10-10N by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10-10N EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $31.20 $42.80
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10,000 Up to 10,000
User I/Os 172 172
Logic Elements / LABs 16 Logic Array Blocks β€”
Propagation Delay (tPD) 10 ns (-10 speed grade) β€”
Maximum Frequency (fCNT) 87 MHz β€”
Supply Voltage - Core (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V β€”
Process Technology CMOS EEPROM CMOS EEPROM
In-System Programmability Yes, IEEE Std. 1532 compliant β€”
Boundary-Scan (JTAG) Yes, IEEE 1149.1 β€”
PCI-SIG Compliance PCI Local Bus Specification Rev 2.2 (at -10 speed grade) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) 0 C to 70 C (commercial)
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount β€”
Lead-Free / RoHS [DATA_NEEDED: RoHS status] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 16
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
Speed Grade β€” -10
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)
RoHS Status β€” [DATA_NEEDED: RoHS status not in verified web data]

Datasheets & Resources

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