EPM3512AQC208-10-10N vs EPM3512AQC208-10S Comparison
Detailed side-by-side comparison of EPM3512AQC208-10-10N by Altera and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N Obsolete
Specification Comparison
| Parameter | EPM3512AQC208-10-10N | EPM3512AQC208-10S |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $31.20 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 1750 |
| User I/Os | 172 | 208 |
| Logic Elements / LABs | 16 Logic Array Blocks | β |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | β |
| Maximum Frequency (fCNT) | 87 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | β |
| Process Technology | CMOS EEPROM | EEPROM-based CMOS |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | β |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | Yes (1149.1 compliant) |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0C to +70C (commercial) |
| Package | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin FineLine BGA-256 |
| Mounting Type | Surface Mount | β |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 32 (16 macrocells each) |
| Speed Grade | β | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | β | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | β | 3.3 V |
| Supply Voltage - VCCIO (I/O) | β | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | β | CMOS EEPROM |
| In-System Programmability (ISP) | β | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | β | Yes (PCI Local Bus Specification Rev 2.2) |
| Program/Erase Endurance | β | 100 cycles minimum |
| Logic Family | β | CMOS |
| RoHS Status | β | [DATA_NEEDED: rohs_status] |