EPM3512AQC208-10 vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10 by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10 EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $22.10 $4.62
Family MAX 3000A β€”
Usable Gates 10,000 10,000
Macrocells 512 β€”
Logic Array Blocks (LABs) 32 β€”
User I/Os 208 β€”
Propagation Delay (tPD) 7.5 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (IEEE Std. 1532) β€”
JTAG Boundary Scan Yes (IEEE 1149.1) β€”
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) β€”
Package 208-pin PQFP β€”
Operating Temperature 0C to +70 C (commercial) 0C to +70C (Commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Maximum Counter Frequency β€” 227.3 MHz
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
Mounting Type β€” Surface Mount
ISP Compliance β€” IEEE Std. 1532
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
I/O Tolerance β€” 5 V tolerant, MultiVolt interface

Datasheets & Resources

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