EPM3512AQC208-10 vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10 by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-10

EPM3512AQC208-10 - MAX 3000A CPLD 512 Macrocells | Intel/Altera

EPM3512AQC208-10 Obsolete
Intel
EPM3512AQC208-10N

EPM3512AQC208-10N - 512-MacroCell MAX 3000A CPLD, 208-PQFP | Intel

EPM3512AQC208-10N Obsolete

Specification Comparison

Parameter EPM3512AQC208-10 EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $22.10 $42.80
Family MAX 3000A MAX 3000A
Usable Gates 10,000 Up to 10,000
Macrocells 512 512
Logic Array Blocks (LABs) 32 16
User I/Os 208 172
Propagation Delay (tPD) 7.5 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (IEEE Std. 1532) β€”
JTAG Boundary Scan Yes (IEEE 1149.1) β€”
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) β€”
Package 208-pin PQFP 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0C to +70 C (commercial) 0 C to 70 C (commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: RoHS status not in verified web data]
Device Type β€” CPLD (Complex Programmable Logic Device)
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
Speed Grade β€” -10
Process Technology β€” CMOS EEPROM
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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