EPM3512AQC208-10 vs EPM3512AQC208-10NS Comparison
Detailed side-by-side comparison of EPM3512AQC208-10 by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-10NS - MAX 3000A 512-Macro CPLD, 208-PQFP | Altera
EPM3512AQC208-10NS β ActiveSpecification Comparison
| Parameter | EPM3512AQC208-10 | EPM3512AQC208-10NS |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.10 | $32.40 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | 10,000 |
| Macrocells | 512 | β |
| Logic Array Blocks (LABs) | 32 | 12 |
| User I/Os | 208 | 172 |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Frequency (fCNT) | 116.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| In-System Programmability | Yes (IEEE Std. 1532) | β |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | β |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | β |
| Package | 208-pin PQFP | 208-pin PQFP |
| Operating Temperature | 0C to +70 C (commercial) | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: rohs status] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 512 |
| Pin-to-Pin Delay (tPD) | β | 10 ns (speed grade -10) |
| Internal Counter Frequency | β | 227.3 MHz max |
| Propagation Delay | β | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Logic Family | β | CMOS, EEPROM-based |
| Configuration | β | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | β | IEEE Std. 1532 |
| Mounting Type | β | Surface Mount |