EPM3512AQC208-10 vs EPM3512AQC208-15N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10 by Altera and EPM3512AQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-10

EPM3512AQC208-10 - MAX 3000A CPLD 512 Macrocells | Intel/Altera

EPM3512AQC208-10 Obsolete
Altera
EPM3512AQC208-15N

EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-10 EPM3512AQC208-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $22.10 $20.50
Family MAX 3000A MAX 3000A
Usable Gates 10,000 β€”
Macrocells 512 β€”
Logic Array Blocks (LABs) 32 16
User I/Os 208 β€”
Propagation Delay (tPD) 7.5 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
In-System Programmability Yes (IEEE Std. 1532) Yes (IEEE Std. 1532 compliant)
JTAG Boundary Scan Yes (IEEE 1149.1) β€”
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) β€”
Package 208-pin PQFP PQFP-208 (QC208)
Operating Temperature 0C to +70 C (commercial) 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: RoHS status]
Device Type β€” CPLD - Complex Programmable Logic Device
Macro Cells β€” 512
Maximum User I/O Pins β€” 172
Typical Usable Gates β€” 12,000
Number of Logic Elements β€” 512
Pin-to-Pin Delay (tPD) β€” 15 ns
Operating Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V (MultiVolt)
Programmable I/O Standards β€” LVTTL, LVCMOS, PCI (with external resistor)
JTAG Support β€” Yes (BST/Boundary-Scan Test)
Mounting Type β€” Surface Mount

Datasheets & Resources

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