EPM3512AQC208-10 vs EPM3512AQC208-3 Comparison

Detailed side-by-side comparison of EPM3512AQC208-10 by Altera and EPM3512AQC208-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-10

EPM3512AQC208-10 - MAX 3000A CPLD 512 Macrocells | Intel/Altera

EPM3512AQC208-10 Obsolete
Altera
EPM3512AQC208-3

EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera

EPM3512AQC208-3 ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-10 EPM3512AQC208-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $22.10 $27.80
Family MAX 3000A MAX 3000A
Usable Gates 10,000 β€”
Macrocells 512 512
Logic Array Blocks (LABs) 32 16 (32 macrocells each)
User I/Os 208 β€”
Propagation Delay (tPD) 7.5 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (IEEE Std. 1532) Yes (IEEE Std. 1532 compliant)
JTAG Boundary Scan Yes (IEEE 1149.1) β€”
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) β€”
Package 208-pin PQFP PQFP-208
Operating Temperature 0C to +70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
RoHS Status [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: confirm from datasheet]
Device Type β€” CPLD (Complex Programmable Logic Device)
Maximum User I/O Pins β€” 172
Speed Grade β€” -3
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Bank Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (multiVolt)
Boundary-Scan Test β€” Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles β€” 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration β€” Yes (EEPROM-based)
Mounting Type β€” Surface Mount
MSL Level β€” [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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