EPM3512AQC208-10N vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3256AQC208-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $42.80 $4.62
Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 β€”
Usable Gates Up to 10,000 10,000
Logic Array Blocks (LABs) 16 β€”
User I/Os 172 β€”
Package 208-pin PQFP (Plastic Quad Flat Pack) β€”
Supply Voltage 3.3 V β€”
Pin-to-Pin Delay 4.5 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz β€”
Speed Grade -10 β€”
Process Technology CMOS EEPROM β€”
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant β€”
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) β€”
Operating Temperature 0 C to 70 C (commercial) 0C to +70C (Commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Maximum Counter Frequency β€” 227.3 MHz
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
Mounting Type β€” Surface Mount
ISP Compliance β€” IEEE Std. 1532
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
I/O Tolerance β€” 5 V tolerant, MultiVolt interface

Datasheets & Resources

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