EPM3512AQC208-10N vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3512AQC208-10NS
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $42.80 $32.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 β€”
Usable Gates Up to 10,000 10,000
Logic Array Blocks (LABs) 16 12
User I/Os 172 172
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP
Supply Voltage 3.3 V β€”
Pin-to-Pin Delay 4.5 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz β€”
Speed Grade -10 β€”
Process Technology CMOS EEPROM β€”
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant β€”
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) β€”
Operating Temperature 0 C to 70 C (commercial) 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: rohs status]
Macro Cells β€” 512
Pin-to-Pin Delay (tPD) β€” 10 ns (speed grade -10)
Internal Counter Frequency β€” 227.3 MHz max
Propagation Delay β€” 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Logic Family β€” CMOS, EEPROM-based
Configuration β€” Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
ISP Standard β€” IEEE Std. 1532
Mounting Type β€” Surface Mount

Datasheets & Resources

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