EPM3512AQC208-10N vs EPM3512AQC208-10S Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3512AQC208-10S
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $42.80 $9.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates Up to 10,000 1750
Logic Array Blocks (LABs) 16 32 (16 macrocells each)
User I/Os 172 208
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin FineLine BGA-256
Supply Voltage 3.3 V β€”
Pin-to-Pin Delay 4.5 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz β€”
Speed Grade -10 -10 (tPD1 = 7.5 ns)
Process Technology CMOS EEPROM EEPROM-based CMOS
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant β€”
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) β€”
Operating Temperature 0 C to 70 C (commercial) 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: rohs_status]
Propagation Delay (tPD1) β€” 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) β€” 3.3 V
Supply Voltage - VCCIO (I/O) β€” 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology β€” CMOS EEPROM
In-System Programmability (ISP) β€” Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance β€” Yes (PCI Local Bus Specification Rev 2.2)
Boundary-Scan (JTAG) β€” Yes (1149.1 compliant)
Program/Erase Endurance β€” 100 cycles minimum
Logic Family β€” CMOS

Datasheets & Resources

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