EPM3512AQC208-10N vs EPM3512AQC208-7 Comparison
Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndSpecification Comparison
| Parameter | EPM3512AQC208-10N | EPM3512AQC208-7 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $42.80 | $41.72 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | β |
| User I/Os | 172 | 172 |
| Package | 208-pin PQFP (Plastic Quad Flat Pack) | 208-Pin PQFP (FQFP, gull-wing) |
| Supply Voltage | 3.3 V | β |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | β |
| Maximum Internal Frequency | 227.3 MHz | β |
| Speed Grade | -10 | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM, 0.30 um |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | β |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | β |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | β |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to +70 C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status not in verified web data] | Compliant |
| Propagation Delay (tPD) | β | 7.5 ns |
| Counter Frequency (fCNT) | β | 116.3 MHz |
| Logic Elements / LEs | β | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Standards Supported | β | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Programming | β | In-System Programmable via JTAG (IEEE Std. 1532) |
| Lead-Free | β | Yes |