EPM3512AQC208-10NS vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10NS by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10NS EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $32.40 $42.80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 512 β€”
Usable Gates 10,000 Up to 10,000
Logic Array Blocks (LABs) 12 16
User I/Os 172 172
Pin-to-Pin Delay (tPD) 10 ns (speed grade -10) β€”
Internal Counter Frequency 227.3 MHz max β€”
Propagation Delay 7.5 ns (datasheet figure) β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) β€”
Logic Family CMOS, EEPROM-based β€”
Configuration Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) β€”
Package 208-pin PQFP 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0C to +70C (commercial) 0 C to 70 C (commercial)
ISP Standard IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status not in verified web data]
Mounting Type Surface Mount β€”
Macrocells β€” 512
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
Speed Grade β€” -10
Process Technology β€” CMOS EEPROM
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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