EPM3512AQC208-10NS vs EPM3512AQC208-2 Comparison

Detailed side-by-side comparison of EPM3512AQC208-10NS by Altera and EPM3512AQC208-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10NS EPM3512AQC208-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $32.40 $18.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macro Cells 512 β€”
Usable Gates 10,000 β€”
Logic Array Blocks (LABs) 12 16
User I/Os 172 β€”
Pin-to-Pin Delay (tPD) 10 ns (speed grade -10) β€”
Internal Counter Frequency 227.3 MHz max β€”
Propagation Delay 7.5 ns (datasheet figure) β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) β€”
Logic Family CMOS, EEPROM-based β€”
Configuration Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) β€”
Package 208-pin PQFP PQFP-208 (QC)
Operating Temperature 0C to +70C (commercial) β€”
ISP Standard IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: rohs status] Non-compliant (legacy PQFP)
Mounting Type Surface Mount Surface Mount
Macrocells β€” 512
User I/O Pins β€” 172
Speed Grade β€” -2
Supply Voltage (Core) β€” 3.3 V
Output Drive Voltage β€” 2.5 V / 3.3 V programmable
Input Voltage Tolerance β€” 2.5 V / 3.3 V / 5.0 V
Process Technology β€” 0.30 Β΅m EEPROM
Program/Erase Endurance β€” 100 cycles (typical)
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
User I/O Banks β€” 4
Operating Temperature Range β€” Commercial (0C to +70C)
Lead-Free β€” No (SnPb lead finish)
Security Bit β€” Yes (programmable)

Datasheets & Resources

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