EPM3512AQC208-10S vs EPM3512AQ208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQ208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQ208-10N

EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera

EPM3512AQ208-10N βœ“ Active

Specification Comparison

Parameter EPM3512AQC208-10S EPM3512AQ208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $21.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates 1750 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) 32
Package 208-pin FineLine BGA-256 208-pin PQFP
User I/Os 208 172
Speed Grade -10 (tPD1 = 7.5 ns) -10 (10 ns pin-to-pin delay)
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) β€”
Supply Voltage - VCCINT (internal) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) β€”
Programming Technology CMOS EEPROM β€”
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) β€”
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) β€”
Operating Temperature 0C to +70C (commercial) β€”
Boundary-Scan (JTAG) Yes (1149.1 compliant) β€”
Program/Erase Endurance 100 cycles minimum β€”
Logic Family CMOS β€”
Process Technology EEPROM-based CMOS CMOS EEPROM
RoHS Status [DATA_NEEDED: rohs_status] unknown
Pin-to-Pin Delay (tPD) β€” 4.5 ns (typical)
Maximum Frequency (fCNT) β€” 227.3 MHz
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V, 3.3 V, or 5.0 V
Programming Interface β€” IEEE Std. 1532 (JTAG) ISP
Operating Temperature (Industrial) β€” -40 C to +85 C
Mounting Type β€” Surface Mount

Datasheets & Resources

Browse All Products Create BOM Request Quote