EPM3512AQC208-10S vs EPM3512AQC20-10 Comparison
Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQC20-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC208-10S | EPM3512AQC20-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $21.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 1750 | β |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 16 |
| Package | 208-pin FineLine BGA-256 | PQFP-240 (QC20 designation per Altera ordering code) |
| User I/Os | 208 | β |
| Speed Grade | -10 (tPD1 = 7.5 ns) | β |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | β |
| Supply Voltage - VCCINT (internal) | 3.3 V | β |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | β |
| Programming Technology | CMOS EEPROM | β |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | β |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | β |
| Program/Erase Endurance | 100 cycles minimum | β |
| Logic Family | CMOS | β |
| Process Technology | EEPROM-based CMOS | 0.30 Β΅m EEPROM CMOS |
| RoHS Status | [DATA_NEEDED: rohs_status] | Compliant (lead-free PQFP package) |
| Macrocells per LAB | β | 32 |
| User I/O Pins | β | 100 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Frequency (fCNT) | β | 116.3 MHz |
| Supply Voltage VCCINT | β | 5.0 V |
| MultiVolt I/O Voltages | β | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | β | IEEE 1149.1 (JTAG) - In-System Programmable |