EPM3512AQC208-10S vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM3512AQC208-10N

EPM3512AQC208-10N - 512-MacroCell MAX 3000A CPLD, 208-PQFP | Intel

EPM3512AQC208-10N Obsolete

Specification Comparison

Parameter EPM3512AQC208-10S EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $42.80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates 1750 Up to 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
Package 208-pin FineLine BGA-256 208-pin PQFP (Plastic Quad Flat Pack)
User I/Os 208 172
Speed Grade -10 (tPD1 = 7.5 ns) -10
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) β€”
Supply Voltage - VCCINT (internal) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) β€”
Programming Technology CMOS EEPROM β€”
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) β€”
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) β€”
Operating Temperature 0C to +70C (commercial) 0 C to 70 C (commercial)
Boundary-Scan (JTAG) Yes (1149.1 compliant) β€”
Program/Erase Endurance 100 cycles minimum β€”
Logic Family CMOS β€”
Process Technology EEPROM-based CMOS CMOS EEPROM
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status not in verified web data]
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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