EPM3512AQC208-10S vs EPM3512AQC208-2 Comparison

Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQC208-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10S EPM3512AQC208-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $18.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 1750 β€”
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
Package 208-pin FineLine BGA-256 PQFP-208 (QC)
User I/Os 208 β€”
Speed Grade -10 (tPD1 = 7.5 ns) -2
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) β€”
Supply Voltage - VCCINT (internal) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) β€”
Programming Technology CMOS EEPROM β€”
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) β€”
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) β€”
Operating Temperature 0C to +70C (commercial) β€”
Boundary-Scan (JTAG) Yes (1149.1 compliant) β€”
Program/Erase Endurance 100 cycles minimum 100 cycles (typical)
Logic Family CMOS β€”
Process Technology EEPROM-based CMOS 0.30 Β΅m EEPROM
RoHS Status [DATA_NEEDED: rohs_status] Non-compliant (legacy PQFP)
User I/O Pins β€” 172
Supply Voltage (Core) β€” 3.3 V
Output Drive Voltage β€” 2.5 V / 3.3 V programmable
Input Voltage Tolerance β€” 2.5 V / 3.3 V / 5.0 V
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
User I/O Banks β€” 4
Operating Temperature Range β€” Commercial (0C to +70C)
Mounting Type β€” Surface Mount
Lead-Free β€” No (SnPb lead finish)
Security Bit β€” Yes (programmable)

Datasheets & Resources

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