EPM3512AQC208-2 vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC208-2 by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-2 EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $18.75 $32.40
Family MAX 3000A MAX 3000A
Macrocells 512 β€”
User I/O Pins 172 β€”
Logic Array Blocks (LABs) 16 12
Speed Grade -2 β€”
Package PQFP-208 (QC) 208-pin PQFP
Supply Voltage (Core) 3.3 V β€”
Output Drive Voltage 2.5 V / 3.3 V programmable β€”
Input Voltage Tolerance 2.5 V / 3.3 V / 5.0 V β€”
Process Technology 0.30 Β΅m EEPROM β€”
Program/Erase Endurance 100 cycles (typical) β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
User I/O Banks 4 β€”
Operating Temperature Range Commercial (0C to +70C) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status Non-compliant (legacy PQFP) [DATA_NEEDED: rohs status]
Lead-Free No (SnPb lead finish) β€”
Security Bit Yes (programmable) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 512
Usable Gates β€” 10,000
User I/Os β€” 172
Pin-to-Pin Delay (tPD) β€” 10 ns (speed grade -10)
Internal Counter Frequency β€” 227.3 MHz max
Propagation Delay β€” 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Logic Family β€” CMOS, EEPROM-based
Configuration β€” Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
Operating Temperature β€” 0C to +70C (commercial)
ISP Standard β€” IEEE Std. 1532

Datasheets & Resources

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