EPM3512AQC208-3 vs EPM3512AQC208-10 Comparison
Detailed side-by-side comparison of EPM3512AQC208-3 by Altera and EPM3512AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-3
EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera
EPM3512AQC208-3 β Last Time BuyAltera
EPM3512AQC208-10
EPM3512AQC208-10 - MAX 3000A CPLD 512 Macrocells | Intel/Altera
EPM3512AQC208-10 ObsoleteSpecification Comparison
| Parameter | EPM3512AQC208-3 | EPM3512AQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.80 | $22.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 32 |
| Maximum User I/O Pins | 172 | β |
| Package | PQFP-208 | 208-pin PQFP |
| Speed Grade | -3 | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Bank Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | β |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | Yes (IEEE Std. 1532) |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 / JTAG) | β |
| Program/Erase Cycles | 100 minimum [DATA_NEEDED: exact datasheet figure] | β |
| Non-Volatile Configuration | Yes (EEPROM-based) | β |
| Operating Temperature | [DATA_NEEDED: industrial/commercial grade range] | 0C to +70 C (commercial) |
| RoHS Status | [DATA_NEEDED: confirm from datasheet] | [DATA_NEEDED: RoHS status not in verified data] |
| Mounting Type | Surface Mount | β |
| MSL Level | [DATA_NEEDED: moisture sensitivity level] | β |
| Usable Gates | β | 10,000 |
| User I/Os | β | 208 |
| Propagation Delay (tPD) | β | 7.5 ns |
| Maximum Frequency (fCNT) | β | 116.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| JTAG Boundary Scan | β | Yes (IEEE 1149.1) |
| PCI Compliance | β | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |