EPM3512AQC208-3 vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-3 by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-3 EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.80 $42.80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 (32 macrocells each) 16
Maximum User I/O Pins 172 β€”
Package PQFP-208 208-pin PQFP (Plastic Quad Flat Pack)
Speed Grade -3 -10
Supply Voltage - Core (VCCINT) 3.3 V β€”
I/O Bank Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) β€”
In-System Programmability Yes (IEEE Std. 1532 compliant) β€”
Boundary-Scan Test Yes (IEEE Std. 1149.1 / JTAG) β€”
Program/Erase Cycles 100 minimum [DATA_NEEDED: exact datasheet figure] β€”
Non-Volatile Configuration Yes (EEPROM-based) β€”
Operating Temperature [DATA_NEEDED: industrial/commercial grade range] 0 C to 70 C (commercial)
RoHS Status [DATA_NEEDED: confirm from datasheet] [DATA_NEEDED: RoHS status not in verified web data]
Mounting Type Surface Mount β€”
MSL Level [DATA_NEEDED: moisture sensitivity level] β€”
Usable Gates β€” Up to 10,000
User I/Os β€” 172
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
Process Technology β€” CMOS EEPROM
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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