EPM3512AQC208-3N vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-3N EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $4.62
Family MAX 3000A β€”
Macrocells 512 β€”
User I/O Pins 172 β€”
Logic Array Blocks (LABs) 16 β€”
Macrocells per LAB 32 β€”
Pin-to-Pin Logic Delay 3 ns (speed grade -3) β€”
Global Clock Setup Time [DATA_NEEDED: actual tSU at 3 ns grade] β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) β€”
Operating Temperature 0C to +70C (commercial) 0C to +70C (Commercial)
Package PQFP-208 β€”
Mounting Type Surface Mount Surface Mount
Programming Technology EEPROM (non-volatile, in-system programmable) β€”
JTAG / Boundary Scan IEEE 1149.1 compliant β€”
ISP Compliance IEEE Std. 1532 IEEE Std. 1532
RoHS Status [DATA_NEEDED: not stated in retrieved snippets] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Lead-Free / Halogen-Free [DATA_NEEDED] β€”
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Usable Gates β€” 10,000
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Maximum Counter Frequency β€” 227.3 MHz
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
I/O Tolerance β€” 5 V tolerant, MultiVolt interface

Datasheets & Resources

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