EPM3512AQC208-3N vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-3N EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $32.40
Family MAX 3000A MAX 3000A
Macrocells 512 β€”
User I/O Pins 172 β€”
Logic Array Blocks (LABs) 16 12
Macrocells per LAB 32 β€”
Pin-to-Pin Logic Delay 3 ns (speed grade -3) β€”
Global Clock Setup Time [DATA_NEEDED: actual tSU at 3 ns grade] β€”
Core Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Package PQFP-208 208-pin PQFP
Mounting Type Surface Mount Surface Mount
Programming Technology EEPROM (non-volatile, in-system programmable) β€”
JTAG / Boundary Scan IEEE 1149.1 compliant β€”
ISP Compliance IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: not stated in retrieved snippets] [DATA_NEEDED: rohs status]
Lead-Free / Halogen-Free [DATA_NEEDED] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 512
Usable Gates β€” 10,000
User I/Os β€” 172
Pin-to-Pin Delay (tPD) β€” 10 ns (speed grade -10)
Internal Counter Frequency β€” 227.3 MHz max
Propagation Delay β€” 7.5 ns (datasheet figure)
Logic Family β€” CMOS, EEPROM-based
Configuration β€” Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
ISP Standard β€” IEEE Std. 1532

Datasheets & Resources

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