EPM3512AQC208-3N vs EPM3512AQC208-10S Comparison
Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC208-3N | EPM3512AQC208-10S |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | β |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Macrocells per LAB | 32 | β |
| Pin-to-Pin Logic Delay | 3 ns (speed grade -3) | β |
| Global Clock Setup Time | [DATA_NEEDED: actual tSU at 3 ns grade] | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | PQFP-208 | 208-pin FineLine BGA-256 |
| Mounting Type | Surface Mount | β |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | CMOS EEPROM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| ISP Compliance | IEEE Std. 1532 | β |
| RoHS Status | [DATA_NEEDED: not stated in retrieved snippets] | [DATA_NEEDED: rohs_status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED] | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 1750 |
| User I/Os | β | 208 |
| Speed Grade | β | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | β | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | β | 3.3 V |
| Supply Voltage - VCCIO (I/O) | β | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | β | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | β | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | β | Yes (1149.1 compliant) |
| Program/Erase Endurance | β | 100 cycles minimum |
| Logic Family | β | CMOS |
| Process Technology | β | EEPROM-based CMOS |