EPM3512AQC208-3N vs EPM3512AQC208-7N Comparison
Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N β Last Time BuySpecification Comparison
| Parameter | EPM3512AQC208-3N | EPM3512AQC208-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $41.41 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | β |
| User I/O Pins | 172 | β |
| Logic Array Blocks (LABs) | 16 | 32 |
| Macrocells per LAB | 32 | 16 |
| Pin-to-Pin Logic Delay | 3 ns (speed grade -3) | β |
| Global Clock Setup Time | [DATA_NEEDED: actual tSU at 3 ns grade] | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) | β |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to +70 Β°C (commercial) |
| Package | PQFP-208 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| Mounting Type | Surface Mount | β |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | β |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| ISP Compliance | IEEE Std. 1532 | β |
| RoHS Status | [DATA_NEEDED: not stated in retrieved snippets] | Compliant |
| Lead-Free / Halogen-Free | [DATA_NEEDED] | β |
| Logic Capacity | β | 512 macrocells, 10,000 usable gates |
| User I/Os | β | 172 |
| Propagation Delay (tPD) | β | 7.5 ns |
| Maximum Frequency (fCNT) | β | 116.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | β | 4 (MultiVolt) |
| Supported I/O Standards | β | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | β | 0.30 Β΅m CMOS EEPROM |
| Configuration | β | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | β | IEEE 1149.1 BST + IEEE 1532 ISP |
| Speed Grade | β | -7 |