EPM3512AQC208-7 vs EPM3512AQC208-2 Comparison

Detailed side-by-side comparison of EPM3512AQC208-7 by Intel and EPM3512AQC208-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-2

EPM3512AQC208-2 - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera

EPM3512AQC208-2 Obsolete

Specification Comparison

Parameter EPM3512AQC208-7 EPM3512AQC208-2
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $41.72 $18.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 10,000 β€”
Propagation Delay (tPD) 7.5 ns β€”
Counter Frequency (fCNT) 116.3 MHz β€”
User I/Os 172 β€”
Logic Elements / LEs N/A (CPLD macrocell architecture) β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) β€”
Package 208-Pin PQFP (FQFP, gull-wing) PQFP-208 (QC)
Operating Temperature 0 C to +70 C (commercial) β€”
Programming In-System Programmable via JTAG (IEEE Std. 1532) β€”
Process Technology CMOS EEPROM, 0.30 um 0.30 Β΅m EEPROM
RoHS Status Compliant Non-compliant (legacy PQFP)
Lead-Free Yes No (SnPb lead finish)
User I/O Pins β€” 172
Logic Array Blocks (LABs) β€” 16
Speed Grade β€” -2
Supply Voltage (Core) β€” 3.3 V
Output Drive Voltage β€” 2.5 V / 3.3 V programmable
Input Voltage Tolerance β€” 2.5 V / 3.3 V / 5.0 V
Program/Erase Endurance β€” 100 cycles (typical)
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
User I/O Banks β€” 4
Operating Temperature Range β€” Commercial (0C to +70C)
Mounting Type β€” Surface Mount
Security Bit β€” Yes (programmable)

Datasheets & Resources

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