EPM3512AQC208-7 vs EPM3512AQC208-3N Comparison

Detailed side-by-side comparison of EPM3512AQC208-7 by Intel and EPM3512AQC208-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-7 EPM3512AQC208-3N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $41.72 $16.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 10,000 β€”
Propagation Delay (tPD) 7.5 ns β€”
Counter Frequency (fCNT) 116.3 MHz β€”
User I/Os 172 β€”
Logic Elements / LEs N/A (CPLD macrocell architecture) β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) β€”
Package 208-Pin PQFP (FQFP, gull-wing) PQFP-208
Operating Temperature 0 C to +70 C (commercial) 0C to +70C (commercial)
Programming In-System Programmable via JTAG (IEEE Std. 1532) β€”
Process Technology CMOS EEPROM, 0.30 um β€”
RoHS Status Compliant [DATA_NEEDED: not stated in retrieved snippets]
Lead-Free Yes β€”
User I/O Pins β€” 172
Logic Array Blocks (LABs) β€” 16
Macrocells per LAB β€” 32
Pin-to-Pin Logic Delay β€” 3 ns (speed grade -3)
Global Clock Setup Time β€” [DATA_NEEDED: actual tSU at 3 ns grade]
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Mounting Type β€” Surface Mount
Programming Technology β€” EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan β€” IEEE 1149.1 compliant
ISP Compliance β€” IEEE Std. 1532
Lead-Free / Halogen-Free β€” [DATA_NEEDED]

Datasheets & Resources

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