EPM3512AQC208-7 vs EPM3512AQC208-7N Comparison

Detailed side-by-side comparison of EPM3512AQC208-7 by Intel and EPM3512AQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-7N

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-7 EPM3512AQC208-7N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $41.72 $41.41
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 β€”
Usable Gates 10,000 β€”
Propagation Delay (tPD) 7.5 ns 7.5 ns
Counter Frequency (fCNT) 116.3 MHz β€”
User I/Os 172 172
Logic Elements / LEs N/A (CPLD macrocell architecture) β€”
Supply Voltage (VCCINT) 3.3 V 3.3 V (3.0 V to 3.6 V)
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) β€”
Package 208-Pin PQFP (FQFP, gull-wing) 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
Operating Temperature 0 C to +70 C (commercial) 0 Β°C to +70 Β°C (commercial)
Programming In-System Programmable via JTAG (IEEE Std. 1532) β€”
Process Technology CMOS EEPROM, 0.30 um 0.30 Β΅m CMOS EEPROM
RoHS Status Compliant Compliant
Lead-Free Yes β€”
Logic Capacity β€” 512 macrocells, 10,000 usable gates
Logic Array Blocks (LABs) β€” 32
Macrocells per LAB β€” 16
Maximum Frequency (fCNT) β€” 116.3 MHz
I/O Bank Count β€” 4 (MultiVolt)
Supported I/O Standards β€” 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Configuration β€” Non-volatile EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE 1149.1 BST + IEEE 1532 ISP
Speed Grade β€” -7

Datasheets & Resources

Browse All Products Create BOM Request Quote